The present invention relates to integrated circuits and packaged integrated circuits and, more particularly, to a packaged integrated circuit formed using two separate leadframes.
An integrated circuit (IC) die is a small device formed on a semiconductor wafer, such as a silicon wafer. A leadframe is a metal frame that usually includes a paddle that supports an IC die that has been cut from the wafer. The leadframe has lead fingers that provide external electrical connections. That is, the die is attached to the die paddle and then bonding pads of the die are connected to the lead fingers via wire bonding or flip chip bumping to provide the external electrical connections. Encapsulating the die and wire bonds or flip chip bump with a protective material forms a package. Depending on the package type, the external electrical connections may be used as-is, such as in a Thin Small Outline Package (TSOP), or further processed, such as by attaching spherical solder balls for a Ball Grid Array (BGA). These terminal points allow the die to be electrically connected with other circuits, such as on a printed circuit board.
Use of packaged ICs is widespread. Moreover, the size and cost of electronic devices puts continuous pressure on the need for small, yet less costly packaged ICs. Furthermore, for high bandwidth RF devices and high operating frequency devices, there is a push for shorter electrical paths inside the IC package. Flip chip bonding can replace the traditional wire bonding interconnection. Thus, it is desirable to provide an inexpensive method of flip chip interconnection packaging ICs. It also is desirable to have a method of decreasing the size of such packaged ICs.